莊紹勳 講座教授(Steve S. Chung, Chair Professor)

地址:新竹市大學路1001號工程四館 501室

實驗室: 工程四館 411室 03-5712121 分機 54224

(mailing address)
Department of Electronics Engineering
National Chiao Tung University
1001 University Road, Hsinchu 300
Tel: 886-3-573 1830
Fax: 886-3-573 4608



前瞻元件與技術實驗室(Emerging Device and Technology Lab)




        簡歷 (Bios)
        Steve S. Chung received his Ph.D. degree from the University of Illinois at Urbana-Champaign, in Electrical Engineering in 1985. His Ph.D.thesis advisor is the world-famous scholar and CMOS Co-Inventor, Prof. C. T. Sah.
        Currently, he is an NCTU Chair Professor, UMC Research Chair Professor at the National Chiao Tung University (NCTU), where he worked as Dean of International Affairs,between 2007-2008. Between 2004-2005, he was the first Department Head of EECS Honors Program, to promote a new undergraduate program for academic excellence, at NCTU where he has served since 1987. He was a Visiting Professor with the University of California-Merced(2009-2010), a guest Instructor at Stanford (2009) and also a visiting scholar to Stanford University, CA, in 2001. He was also the consultant to both TSMC and UMC on developing CMOS and flash memory technologies. His current research areas include CMOS device technology with emphasis on trigate and Tunneling FET, flash memory technology, resistance memory technology,embedded memory technology, reliability characterization and modeling. He has published more than 250 journal and conference papers, one textbook, and holds about 35 patents. Since 1995, he has personally presented more than 26 times in the world leading IEEE conferences, IEDM and VLSI, with focus on the reliability and technology of strained-CMOS, flash memory devices. In particular, he is the first (from Taiwan) to present the paper at VLSI Technology symposium in 1995. Three highest impact inventions (with both paper publishing and patents) by his team includes: (1) IFCP(Incremental Frequency Charge Pumping), a milestone for the CMOS reliability analysis beyond the 90nm generation. This method can replace the conventional CV method (which has been used for 50 years) in measuring the interface/oxide traps with small dimensions and with gate oxide thickness in the tunneling regime. (2) A unique Ig-RTN transient measurement on the understanding of FET breakdown based on the characterization of traps in the gate dielectric. A third breakdown was discovered, different from the well known soft-breakdown and hard-breakdown. This led to the invention of an OTP structure with vast economic benefit. (3) A new invention of one-transistor nonvolatile memory which will be able to replace conventional Floating Gate since its inception in 1967, as floating gate reaches its scaling limit at around 20nm. These are cornerstones for a sustainable semiconductor industry when the Silicon technology scaling is continuing.
        He is an IEEE Fellow, the current IEEE EDS BoG(Board Governor) member, EDS AdCom member (2004-2009), IEEE Distinguished Lecturer, EDS Regions/Chapters Vice-Chair/Chair, and Editor of J-EDS (2014-), Editor of EDL(2002-2008). He has served on the committees of premiere conferences, e.g., VLSI Technology, IEDM, IRPS, etc. Also, he has been the Technical Program Chair of 2004 and 2015 IPFA, the Technical Program Vice-Chair of SSDM (the largest conference in semiconductor areas in Japan). ED Taipei chapter was awarded the 2002 EDS Chapter of the Year Award under his leadership as the chapter chair. This is a remarkable achievement and milestone to the IEEE societies in Taiwan since the chapter is the first one to receive this honor among those 26 IEEE Taipei chapters at that time. He was awarded 3 times outstanding Research Award for excellence in research, as well as the top-PI in 2003, and the current distinguished NSC Research Fellow, from the National Science Council. He was also granted Distinguished EE Professor and Engineering Professor by the Engineering Societies of Taiwan.
        More recently, he was the recipient of 2013 Pan Wen Yuan award in recognizing his outstanding achievements in the semiconductor research.
        各項榮譽與重要貢獻 (Honors/Awards & Major Achievements)-
        2017 VLSI Technology Symposium, Highlight paper [*]
        潘文淵研究傑出獎(Pan Wen-Yuan Outstanding Research Award, 2013)
        國科會傑出特約研究人員獎(NSC Distinguished esearch Fellow, 2013)
        國科會傑出學者計畫主持人 (NSC Distinguished Research Fellow, 2009-2012)
        IEEE Fellow (for contributions to the reliability of ultra-thin-oxide CMOS devices)
        國科會特約研究人員獎(NSC Research Fellow, 2006-2009)
        國科會三次傑出研究獎(Outstanding Research Award, 1996-2003)
        國科會三次優等研究獎(Excellent Research Award, 1989-1995)
        中國工程師學會傑出工程教授(Distnguished Engineering Professor)
        電機工程師學會傑出電機工程教授(Distinguished EE Professor)
        專利(patents): > 36
        論文發表(published paper): IEEE Journal and Conference Papers (more than 250)
        * E. R. Hsieh, S. S. Chung et al., “First Demonstration of Flash RRAM on Pure CMOS Logic 14nm FinFET Platform Featuring Excellent Immunity to Sneak-path and MLC Capability,” in Symposium on VLSI Technology, pp. 64-65, Kyoto, June 13-17, 2017. A world first FinFET Resistance NVM feasible for embedded memory in advance 14nm platform (A highlight paper)
        IEDM/VLSI論文發表: (First author發表)31篇 (up to 2018.3)
        1995 VLSI Technology 台灣首次上榜論文為本研究群發表 (The first paper contributed from Taiwan)
        1997 VLSI Technology 台灣唯一上榜論文為本研究群發表 (The only paper contributed from Taiwan)
         [Remark 2]
        1995-2016 VLSI Technology 台灣各大學上榜論文統計, 37% 為本研究群發表 (第一作者)
        2002 IEEE EDS Chapter of the Year Award 為莊教授擔任IEEE EDS Taipei Chapter會長期間, 50年來台灣地區分會第一次獲得榮譽 (台灣現有26個IEEE 分會)
        IEDMS Best Paper Award (最佳論文獎) (1996)
        IEDMS Best Paper Award (最佳論文獎) (2010)
        [Remark 1] S. S. Chung et al., in Symposium on VLSI Tech., pp. 74-75, Hawaii, 2002. ( also, US patent, No. 6,746,883)
        [Remark 2] S. S. Chung et al., in Symposium on VLSI Tech., pp. 111-112, Kyoto, 1997.
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