Tel: 886-3-5712121 x 54122
- 1975 : B.S.E.E., National Taiwan University
- 1982 : Ph.D. E.E., University of California, Berkeley
- 1982-1986 :IBM T. J. Watson Research Center, Research Staff Member
- 1986-1988 :IBM T. J. Watson Research Center, Manager, Bipolar VLSI Design
- 1988-2008 :IBM T. J. Watson Research Center, Manager, High-Perf. Circuit Design
- 2008/02 - :Chair Professor,Dept. of Electronic Engineering, Natinal Chiao-Tung University
- 1994 : Fellow, IEEE
- 1994 : Member, New York Academy of Science
- 2008-2013 : 傑出人才講座 (Outstanding Scholar Award), 財團法人傑出人才發展基金會(Foundation for the Advancement of Outstanding Scholarship)
- 2014 : 交大終身講座教授
- High-Performance SRAM Design
- Leakage/Variation/Degradation Tolerant SRAM Circuit Techniques
- Ultra-Low-Power SRAM Design
- Variation/Degradation Monitoring Structures
- Analysis, Evaluation, and Exploration of Novel Circuit Topologies in Scaled/Emerging Technologies
- Bio-Medical Sensing Circuits
- 3D Integrated Circuits
Ching-Te Chuang (S78 - M82 - SM91 - F94) received the B.S.E.E. from National Taiwan University, Taipei, Taiwan in 1975 and Ph.D. degree in Electrical Engineering from University of California, Berkeley, CA in 1982.
From 1977 to 1982 he was a research assistant in the Electronics Research Laboratory, University of California, Berkeley, working on bulk and surface acoustic wave devices. He joined the IBM T. J. Watson Research Center, Yorktown Heights, NY in 1982, working on scaled bipolar devices, technology, and circuits. He studied the scaling properties of epitaxial Schottky barrier diodes, did pioneering works on the perimeter effects of advanced double-poly self-aligned bipolar transistors, and designed the first sub-nanosecond 5-Kb bipolar ECL SRAM. From 1986 to 1988, he was Manager of the Bipolar VLSI Design Group, working on low-power bipolar circuits, high-speed high-density bipolar SRAMs, multi-Gb/s fiber-optic data-link circuits, and scaling issues for bipolar/BiCMOS devices and circuits. Since 1988, he has managed the High Performance Circuit Group, investigating high-performance logic and memory circuits. During early 90’s, when IBM was transitioning from the bipolar based mainframe computer to CMOS microprocessor based system, Dr. Chuang was one of the key managers in setting up series of training classes to successfully retrain physicists, chemists, material scientists, and technology/device developers into custom CMOS circuit designers. Since 1993, his group has been primarily responsible for the circuit design of IBM’s high-performance CMOS microprocessors for enterprise servers, PowerPC workstations, and game/media processors. Since 1996, he has been leading the efforts in evaluating and exploring scaled/emerging technologies, such as PD/SOI, UT/SOI, strained-Si devices, hybrid orientation technology, and multi-gate/FinFET devices, for high-performance logic and SRAM applications. Since 1998, he has been responsible for the Research VLSI TCC (Technology Circuit Co-design), and more recently DFM (Design for Manufacturability) strategy and execution. His group has also been very active and visible in leakage/variation/degradation tolerant circuit and SRAM design techniques. He has received 1 Outstanding Technical Achievement Award, 1 Research Division Outstanding Contribution Award, 5 Research Division Awards, and 12 Invention Achievement Awards from IBM.
Dr. Chuang served on the Device Technology Program Committee for IEDM in 1986 and 1987, and the Program Committee for Symposium on VLSI Circuits from 1992 to 2006. He was the Publication/Publicity Chairman for Symposium on VLSI Technology and Symposium on VLSI Circuits in 1993 and 1994, and the Best Student Paper Award Sub-Committee Chairman for Symposium on VLSI Circuits from 2004 to 2006. He was elected an IEEE Fellow in 1994 “For contributions to high-performance bipolar devices, circuits, and technology". He has authored many invited papers in international journals such as International J. of High Speed Electronics, Proceedings of IEEE, IEEE Circuits and Devices Magazine, and Microelectronics Journal. He has presented numerous plenary, invited or tutorial papers/talks at international conferences such as International SOI Conf., DAC, VLSI-TSA, ISSCC Microprocessor Design Workshop, VLSI Circuit Symposium Short Course, ISQED, ICCAD, APMC, VLSI-DAT, ISCAS, MTDT, WSEAS, VLSI Design/CAD Symp., and International Variability Characterization Workshop, and ISSCC forum, etc.. He was the co-recipient of the Best Paper Awards at the 2000 IEEE International SOI Conference and 2015 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA). He holds 66 U.S. patents with another 20 pending. He has authored or coauthored over 420 papers.
Dr. Chuang took early retirement from IBM to join the Dept. of Electronics Engineering, National Chiao-Tung University, Hsinchu, Taiwan in Feb. 2008, where he is currently a Life Chair Professor. He has received the Outstanding Scholar Award (傑出人才講座) from Foundation for the Advancement of Outstanding Scholarship (財團法人傑出人才發展基金會) in Taiwan for 2008–2013.