Office: ED531; Tel: 886-3-5712121 ext.54142
- Modeling & Evaluation of Exploratory/Beyond-CMOS Devices for Logic/SRAM Applications. These logic devices include FinFET/Trigate, Stacked Nanowire, High-Mobility III-V/Ge Channel, 2D-Material Channel, and Negative-Capacitance FETs.
Prof. Pin Su received his B.S. and M.S. degrees in electronics engineering from National Chiao Tung University, and Ph.D. degree from the Department of Electrical Engineering and Computer Sciences, University of California at Berkeley.
From 1997 to 2003, he conducted his doctoral and postdoctoral research in Silicon-On-Insulator (SOI) devices at Berkeley. He was also one of the major contributors to the unified BSIMSOI model, the first industrial standard SOI MOSFET model for circuit design. Since August 2003, he has been with the Department of Electronics Engineering, National Chiao Tung University, where he is currently a Professor. His research interests include silicon-based nanoelectronics, modeling and design for exploratory/beyond CMOS devices, and circuit-device interaction and co-optimization for low-power applications. He has authored or coauthored over 240 refereed journal and conference papers regarding his research interests.
Prof. Su has served or is serving as the technical committee member of IEDM (2012-2013), SSDM and EDTM, among others.